IMXRT1160AXEC datasheet(62/130 Pages) NXP

Il numero della parte	IMXRT1160AXEC

Spiegazioni elettronici	i.MX RT1160 Crossover Processors Data Sheet for Extended Industrial Products

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i.MX RT1160 Crossover Processors Data Sheet for Extended Industrial Products, Rev. 4, 06/2025

NXP Semiconductors

Electrical characteristics

Figure 17 shows the output timing in ASYNC mode.

Figure 17. SEMC output timing in ASYNC mode

4.5.1.1.2

SEMC output timing in SYNC mode

Table 48 shows SEMC output timing in SYNC mode.

Figure 18 shows the output timing in SYNC mode.

4 WE# low time is configurable by SEMC_*CR0.WEL. WEL field setting value is 0x0 in above table. When WEL is set with value

N, TWEL min time should be ((N + 1) x TCK - 1). See the i.MX RT1160 Reference Manual (IMXRT1160RM) for more detail

about SEMC_*CR0.WEL register field.

Table 48. SEMC output timing in SYNC mode

Symbol

Parameter

Min.

Max.

Unit

Comment

Frequency of operation

—

200

MHz

—

TCK

Internal clock period

—

TDVO

Data output valid time

—

0.6

These timing parameters apply to

Address/Data/DM/CKE/control

signals with SEMC_CLK for

SDRAM.

TDHO

Data output hold time

-0.7

—

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