AD8565/AD8566/AD8567

Rev. D | Page 12 of 16

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MO-187-AA

0.80

0.60

0.40

8°

0°

4

8

1

5

PIN 1

0.65 BSC

SEATING

PLANE

0.38

0.22

1.10 MAX

3.20

3.00

2.80

COPLANARITY

0.10

0.23

0.08

3.20

3.00

2.80

5.15

4.90

4.65

0.15

0.00

0.95

0.85

0.75

Figure 34. 8-Lead Micro Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

COMPLIANT TO JEDEC STANDARDS MO-203-AA

0.30

0.15

0.10 MAX

1.00

0.90

0.70

0.46

0.36

0.26

SEATING

PLANE

0.22

0.08

1.10

0.80

4

5

12

3

PIN 1

0.65 BSC

2.20

2.00

1.80

2.40

2.10

1.80

1.35

1.25

1.15

0.10 COPLANARITY

0.40

0.10

Figure 35. 5-Lead Thin Shrink Small Outline Transistor Package [SC70]

(KS-5)

Dimensions shown in millimeters

4.50

4.40

4.30

14

8

7

1

6.40

BSC

PIN 1

5.10

5.00

4.90

0.65

BSC

SEATING

PLANE

0.15

0.05

0.30

0.19

1.20

MAX

1.05

1.00

0.80

0.20

0.09

8°

0°

0.75

0.60

0.45

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

Figure 36. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters