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CLC001 Scheda tecnica(PDF) 8 Page - National Semiconductor (TI) |
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CLC001 Scheda tecnica(HTML) 8 Page - National Semiconductor (TI) |
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8 / 11 page ![]() Device Operation (Continued) Figure 7 shows an AC-coupled, twisted pair cable applica- tion. It implements a center tap capacitance termination used in conjunction with two 50 Ω resistors to filter common mode noise. R BB set at 5k Ω provides 1.25V of DC bias to each input. PECL or LVPECL drivers may be interfaced to the CLC001 as shown in Figure 8. The voltage divider network will reduce the PECL output to the proper levels. For LVPECL, the 100 Ω series resistors should be removed, since the common mode range inputs of the CLC001 are wide enough to accept LVPECL levels directly. No external DC biasing is required for PECL/LVPECL connections. 10132907 FIGURE 7. Twisted Pair Cable, AC-coupled 10132908 FIGURE 8. PECL, DC-coupled www.national.com 8 |
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