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L6917B Scheda tecnica(PDF) 11 Page - STMicroelectronics |
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L6917B Scheda tecnica(HTML) 11 Page - STMicroelectronics |
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11 / 33 page ![]() 11/33 L6917B which the low-side mosfet is on (OFF Time). During this time, the reaction keeps the pin ISENx and PGNDSx at the same voltage while during the time in which the reading circuitry is off, an internal clamp keeps these two pins at the same voltage sinking from the ISENx pin the necessary current. The proprietary current reading circuit allows a very precise and high bandwidth reading for both positive and negative current. This circuit reproduces the current flowing through the sensing element using a high speed Track & Hold transconductance amplifier. In particular, it reads the current during the second half of the OFF time reducing noise injection into the device due to the mosfet turn-on (See fig. 4). Track time must be at least 200ns to make proper reading of the delivered current. Figure 4. Current Reading Timing (Left) and Circuit (Right) This circuit sources a constant 50 µA current from the PGNDSx pin and keeps the pins ISENx and PGNDSx at the same voltage. Referring to figure 4, the current that flows in the ISENx pin is then given by the following equation: Where RSENSE is an external sense resistor or the rds,on of the low side mosfet and Rg is the transconductance resistor used between ISENx and PGNDSx pins toward the reading points; IPHASE is the current carried by each phase and, in particular, the current measured in the middle of the oscillator period The current information reproduced internally is represented by the second term of the previous equation as follow: Since the current is read in differential mode, also negative current information is kept; this allow the device to check for dangerous returning current between the two phases assuring the complete equalization between the phase's currents. From the current information of each phase, information about the total current delivered (IFB = IINFO1 + IINFO2) and the average current for each phase (IAVG = (IINFO1 + IINFO2)/2 ) is taken. IINFOX is then compared to IAVG to give the correction to the PWM output in order to equalize the current carried by the two phases. The transconductance resistor Rg has to be designed in order to have current information of 25 µA per phase at full nominal load; the over current intervention threshold is set at 140% of the nominal (IINFOx = 35 µA). According to the above relationship, the limiting current (ILIM) for each phase, which has to be placed at one half of the total delivered maximum current, results: An over current is detected when the current flowing into the sense element is greater than 140% of the nominal Rg 50 µµA IISENx Rg LGATEX ISENX PGNDSX ILS1 ILS2 Track & Hold Total current information I ISENx 50 µA R SENSE I PHASE ⋅ R g ---------------------------------------------- + 50 µAI IN FO x + == I IN FO x R SENSE I PHASE ⋅ R g ---------------------------------------------- = I LIM 35 µARg ⋅ R SENSE --------------------------- = Rg I LIM R SENSE ⋅ 35 µA ------------------------------------- = |
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