ADRF5440BCDZ-R7 datasheet(14/18 Pages) AD

14 / 18 page

Data Sheet

ADRF5440

THEORY OF OPERATION

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Rev. A | 14 of 18

RF INPUT AND OUTPUT

The RF ports (RFC, RF1 to RF4) are DC-coupled to 0V, and no DC

blocking is required at the RF ports when the RF line potential is

equal to 0V. The RF ports are internally matched to 50Ω.

The ADRF5440 is bidirectional with equal power handling capabili-

ties. The RF input signal can be applied to the RFC port or the

selected RF throw port.

The insertion loss path conducts the RF signal between the select-

ed RF throw port and the RF common port. The isolation paths

provide high loss between the insertion loss path and the unselect-

ed RF throw ports. The unselected RF ports of the ADRF5440 are

reflective.

The power handling of the ADRF5440 derates with frequency less

than 3GHz and more than 70GHz. See Figure 2 and Figure 3 for

the derating of the RF power towards lower and higher frequencies.

POWER SUPPLY

The ADRF5440 requires a positive supply voltage applied to the

VDD pin and a negative supply voltage applied to the VSS pin.

Bypassing capacitors are recommended on the supply lines to filter

high frequency noise.

The ideal power-up sequence is as follows:

1. Connect to GND.

2. Power up VDD and VSS. Power up VSS after VDD to avoid

current transients on VDD during ramp up.

3. Apply the digital control inputs (V1 and V2). The relative order

of the control inputs is not important. However, powering the

digital control inputs before the VDD supply can inadvertently

forward bias and damage the internal ESD protection struc-

tures. To avoid this damage, use a series 1kΩ resistor to

limit the current flowing into the control pins. Use pull-up or

pull-down resistors if the controller is in a high impedance state

after VDD is powered up and the control pins are not driven to a

valid logic state.

4. Apply an RF input signal.

The ideal power-down sequence is the reverse order of the power-

up sequence.

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