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LMKDB1104FS Scheda tecnica(PDF) 30 Page - Texas Instruments |
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LMKDB1104FS Scheda tecnica(HTML) 30 Page - Texas Instruments |
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30 / 126 page ![]() 6.6 SMBus Timing Requirements 100-kHz CLASS 400-kHz CLASS UNIT MIN MAX MIN MAX fSMB SMBus Operating Frequency 10 100 10 400 kHz fBUF Bus free time between STOP and START condition 4.7 – 1.3 – μs tHD_STA Hold time after (REPEATED) START condition 4.0 – 0.6 – μs tSU_STA REPEATED START condition setup time 4.7 – 0.6 – μs tSU_STO STOP condition setup time 4.0 – 0.6 – μs tHD_DAT Data hold time 0 – 0 – ns tSU_DAT Data setup time 250 – 100 – ns tTIMEOUT Detect clock low timeout 25 35 25 35 ms tLOW Clock low period 4.7 – 1.3 – μs tHIGH Clock high period 4.0 50 0.6 50 μs tLOW_SEXT Cumulative clock low extend time (secondary device) – 25 – 25 ms tLOW_PEXT Cumulative clock low extend time (primary device) – 10 – 10 ms tF Clock/Data Fall Time – 300 – 300 ns tR Clock/Data Rise Time – 1000 – 300 ns tSPIKE Noise spike suppression time – – 0 50 ns tPOR Time in which a device must be operational after power-on reset 500 500 ms 6.7 SBI Timing Requirements MIN MAX UNIT tPERIOD Clock period 40 - ns tSETUP SHFT setup to SBI_CLK rising edge 10 – ns tDSU SBI_IN data setup to SBI_CLK rising edge 5 – ns tDHOLD SBI_IN data hold after SBI_CLK rising edge 2 – ns tDOUT SBI_CLK rising edge to SBI_OUT data valid 2 – ns tLD CLK rising edge to LD# falling edge 10 – ns tOE Delay from LD# falling edge to output enable/disable taking effect 4 10 clocks tSLEW SBI_CLK 20% to 80% slew rate 0.7 4 V/ns 6.8 Timing Diagrams SMBDAT SMBCLK tHD_STA VIH VIL VIH VIL ttBUFt tR tLOW tF tHIGH tHD_DAT tSU_DAT tSU_STA tSU_STO P S P Figure 6-1. SMBus Timing Diagram LMKDB1102, LMKDB1104, LMKDB1104FS LMKDB1108, LMKDB1108FS, LMKDB1112, LMKDB1120, LMKDB1120FS SNAS855F – NOVEMBER 2023 – REVISED NOVEMBER 2025 www.ti.com 30 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: LMKDB1102 LMKDB1104 LMKDB1104FS LMKDB1108 LMKDB1108FS LMKDB1112 LMKDB1120 LMKDB1120FS |
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