4

Current @

TS Pin

VBATT-VDD≥0.2V

Input Bias

Current @

CS Pin

ICS

VCS =5V,

VBATT-VDD≥0.2V

---

---

1.1

uA

Output

Voltage

VO(REG)

4.160

4.20

4.240

V

Current

Regulation

Threshold

VI(SNS)

VI(SNS)=VDD-VCS

100

115

130

mV

Current

Detect

Threshold

V(PRE)

V(PRE)=VDD-VCS

4

12

24

mV

Precharge

Threshold

VO(MIN)

2.7

2.9

3.1

V

Recharge

Threshold

VO(RCH)

VO(REG)-

170mV

VO(REG)-

110mV

VO(REG)-

50mV

V

Charge

Teminated

Current

Detect

Threshold

V(TERM)

V(TERM)=VDD-VCS

2

12

22

mV

Ouput Low

Voltage

@STAT1Pin

VSTAT1(LOW)

IOL =10mA

-----

0.4

0.6

V

Ouput High

Voltage

@STAT1Pin

VSTAT1(HIGH)

IOH=5mA

VDD-0.5V

----

----

V

Ouput Low

Voltage

@STAT2 Pin

VSTAT2(LOW)

IOL =10mA

-----

0.4

0.6

V

Ouput High

Voltage

@STAT2 Pin

VSTAT2(HIGH)

IOH=5mA

VDD-0.5V

----

----

V

Lower

Temperature

Threshold

VTS1*

28

30

32

%VDD

Upper

Temperature

Threshold

VTS2*

68

70

72

%VDD

Note 1.

Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage

to the device. These are for stress ratings. Functional operation of the device at these or

any other conditions beyond those indicated in the operational sections of the

specifications is not implied. Exposure to absolute maximum rating conditions for