Data Sheet

SSM2537

Rev. 0 | Page 7 of 16

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Function

Description

A1

PDAT

Input

PDM Data Signal.

A2

LRSEL

Input

Left/Right Channel Select. Tie to ground for left channel; pull up to VDD for right channel.

A3

OUT−

Output

Inverting Output.

B1

VDD

Supply

Digital Power, 1.8 V.

B2

PVDD

Supply

Amplifier Power, 2.5 V to 5.5 V.

B3

PGND

Ground

Amplifier Ground.

C1

PCLK

Input

PDM Interface Master Clock.

C2

GAIN_FS

Input

Gain and Sample Rate Selection Pin. (Connect to PVDD for typical operation.)

C3

OUT+

Output

Noninverting Output.

TOP VIEW

(BALL SIDE DOWN)

Not to Scale

BALL A1

CORNER

A

3

2

1

B

C

PDAT

OUT–

LRSEL

VDD

PVDD

PGND

PCLK

GAIN_FS

OUT+