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TMS320VC5506 Scheda tecnica(PDF) 87 Page - Texas Instruments |
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TMS320VC5506 Scheda tecnica(HTML) 87 Page - Texas Instruments |
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87 / 120 page ![]() Electrical Specifications 87 October 2006 − Revised January 2008 SPRS375C M23 M37 M22 M36 CLKMEM CEx† BEx‡ EMIF.A[13:0] D[15:0] SDA10 SDRAS SDCAS SDWE M32 M33 MRS MRS Value 0x30§ M26 M27 M28 M29 † The chip enable that becomes active depends on the address being accessed. ‡ All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals remain active until the next access that is not an SDRAM read occurs. § Write burst length = 1 Read latency = 3 Burst type = 0 (serial) Burst length = 1 Figure 5−13. SDRAM MRS Command |
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