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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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STA33013TR Scheda tecnica(PDF) 18 Page - STMicroelectronics |
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STA33013TR Scheda tecnica(HTML) 18 Page - STMicroelectronics |
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18 / 55 page  PLL STA330 18/55 PLL filter Figure 8 shows the PLL filter scheme. Recommended values are R1 = 12.5 k Ω, C1 = 250 pF, and C2 = 82 pF. Figure 8. PLL filter scheme Table 6 on page 10 gives a typical lock time value for the PLL. 6.2 Configuration examples The STA330 PLL can be configured in two ways: " default startup configuration " direct PLL programming The default startup configuration reads the device defaults. With this configuration, it is not necessary to program the PLL dividers directly as some presets are used. In this mode, the oversampling ratio between pins XTI (or MCLK33) and LRCLKI is fixed to 256. The direct PLL programming bypasses the automatic presets allowing direct programming of the PLL dividers. The output PLL frequency can be determined as following: Output division factor: ODF = 2 Relation between input and output clock frequency: FINFIN = FXTI / IDF If register bit PLLCFG0.FRAC_CTRL = 1 FVCO = FINFIN * (LDF + FRACT / 2 16 + 1 / 217) FPHI = FVCO / ODF When register bit PLLCFG0.DITHER_DISABLE[1] = 1, the 1 / 217 factor is not in the multiplication. It is recommended to keep register bit PLLCFG0.DITHER_DISABLE[1] = 0, otherwise there can be spurious signals in the output clock spectrum. C2 R1 C1 Vc Ground |
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