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LNBH24PPR Scheda tecnica(PDF) 6 Page - STMicroelectronics |
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LNBH24PPR Scheda tecnica(HTML) 6 Page - STMicroelectronics |
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6 / 30 page ![]() Introduction LNBH24 6/30 be activated both with the DSQIN pin or the TEN I²C bit. The DSQIN internal circuit activates the 22 kHz tone on the VoTX output with 0.5 cycle ± 25 µs delay from the TTL signal presence on the DSQIN pin, and it stops with 1 cycle ± 25 µs delay after the TTL signal is expired. 2.5 Data encoding through external tone generator (EXTM) In order to improve design flexibility an external tone input pin is available (EXTM). The EXTM is a Logic input pin which activates the 22 kHz tone output, on the VoTX pin, by using the LNBH24 integrated tone generator (similar to the DSQIN pin function). In fact, the output tone waveform characteristics will always be internally controlled by the LNBH24 tone generator and the EXTM signal will be used as a timing control for DiSEqC tone data encoding on the VoTX output. A TTL-compatible 22 kHz signal is required for the proper control of the EXTM pin function. Before sending the TTL signal on the EXTM pin, the VoTX tone generator must be previously enabled through the TTX function (TTX pin or TTX bit set HIGH). As soon as the EXTM internal circuit detects the 22 kHz TTL signal code, it activates the 22 kHz tone on the VoTX output with 1.5 cycles ±25 µs delay from the TTL signal presence on the EXTM pin, and it stops with 2 cycles ±25 µs delay after the TTL signal is expired (see Figure 2). 2.6 I²C interface The main functions of the IC are controlled via I²C BUS by writing 8 bits on the System Register (SR 8 bits in write mode). On the same register there are 8 bits that can be read back (SR 8 bits in read mode) to provide 8 diagnostic functions: five bits will report the diagnostic status of five internal monitoring functions (IMON, VMON, TMON, OTF, OLF), while three will report the last output voltage register status (EN, VSEL, LLC) received by the IC (see the diagnostic functions section). Each section (A/B) has two selectable I²C addresses selectable, respectively, through the ADDR-A and ADDR-B pins (see address pins characteristics Table 10). 2.7 Output voltage selection When the IC sections are in standby mode (EN bit LOW), the power blocks are disabled. When the regulator blocks are active (EN bit HIGH), the output can be logic controlled to be 13 or 18 V by means of the VSEL bit (Voltage SELect) for remote controlling of non-DiSEqC LNBs. Additionally, the LNBH24 is provided with the LLC I2C bit which increase the selected voltage value by +1 V to compensate the excess of voltage drop along the coaxial cable. Figure 2. EXTM timings |
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