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Motore di ricerca datesheet componenti elettronici |
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MFRC522 Scheda tecnica(PDF) 71 Page - NXP Semiconductors |
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MFRC522 Scheda tecnica(HTML) 71 Page - NXP Semiconductors |
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71 / 109 page  112132 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 3.2 — 22 May 2007 71 of 109 NXP Semiconductors MFRC522 Contactless Reader IC 17. Reset and Oscillator Startup Time 17.1 Reset Timing Requirements The reset signal is filtered by a hysteresis circuit and a spike filter (rejects signals shorter than 10 ns) before it enters the digital circuit. In order to perform a reset, the signal has to be low for at least 100 ns. 17.2 Oscillator Startup Time Having set the MFRC522 to a Power-down mode or supplying the IC with XVDD the following figure describes the startup timing for the oscillator. The time tstartup defines the startup time of crystal oscillator circuit. The crystal oscillator startup time is defined by the crystal itself. The tdelay defines the internal delay time of the MFRC522 when the clock signal is stable before the MFRC522 can be addressed. The delay time is calculated as follows: tdelay [μs] = 1024/27.12 = 37.76 μs. The time tosc is defined as the sum of the time tdelay and tstartup. Fig 23. Oscillator Startup time. Device Activation Oscillator Clock Stable Clock Ready t startup t osc t delay t |
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