CE6313 datasheet(19/24 Pages) INTEL

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CE6313

Data Sheet

Intel Corporation

4.3

Primary 2-Wire Bus Timing

Figure 14 - Primary 2-Wire Bus Timing

Where: S = Start

Sr = Restart, i.e., Start without stopping first.

P = Stop

4.4

Crystal Specification

Parallel resonant fundamental frequency (preferred) 9.99 to 16.01 MHz.

Tolerance over operating temperature range ±25 ppm.

Tolerance overall ±50 ppm.

Table 1 - Primary 2-wire bus timing

Parameter: Primary 2-wire bus only

Symbol

Value

Unit

Min.

Max.

CLK1 clock frequency (for XTI

≥10MHz)

fCLK

400

kHz

Bus free time between a STOP and START condition

tBUF

1300

Hold time (repeated) START condition

tHD;STA

600

LOW period of CLK1 clock

tLOW

1300

HIGH period of CLK1 clock

tHIGH

600

Set-up time for a repeated START condition

tSU;STA

600

Data hold time (when input)

tHD;DAT

0ns

Data set-up time

tSU;DAT

100

Rise time of both CLK1 and DATA1 signals

20+0.1Cb1

1. Cb = the total capacitance on either clock or data line in pF.

3002

2. The rise time depends on the external bus pull up resistor and bus capacitance.

Fall time of both CLK1 and DATA1 signals, (100pF to ground)

20+0.1Cb1

300

Set-up time for a STOP condition

tSU;STO

600

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