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TDA7500A Scheda tecnica(PDF) 3 Page - STMicroelectronics |
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TDA7500A Scheda tecnica(HTML) 3 Page - STMicroelectronics |
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3 / 40 page ![]() 3/40 TDA7500A PIN DESCRIPTION N° Name Type Description 1 GND1 Ground pin dedicated to the digital circuitry. 2 VDD1 Supply pin dedicated to the digital circuitry. 3 TESTEN I Test Enable (Input). When low, puts the chip into test mode and muxes the XTI clock to all flip-flops. When TEST_SE is also active, the scan chain shifting is enabled. To be connected to Vdd in operating mode. 4 TESTSE I SCAN Enable (Input). When high with TESTEN also active, controls the shifting of the internal scan chains. When active with TESTEN not active, sets all tri-state outputs into hi-impedance mode. To be connected to GND in operating mode. 5 NRESET I System Reset (Input). A low level applied to NRESET input initializes the IC. 6 SCKM/DSP0_GPIO0 I/O I2C Serial Clock Line (Input/Output)/SPI Bit Clock (Input)/ General Purpose I/O (Input/Output). Clock line for I2C bus. If SPI interface is enabled, behaves as SPI bit clock. Optionally it can be used as general purpose I/O controlled by DSP0. 7 MISOM/DSP0_GPIO1 I/O I2C Serial Data Line (Input/Output)/SPI Master Input Slave Output Serial Data (Input/Output)/General Purpose I/O (Input/ Output). Data line for I2C bus. If SPI is enabled, behaves as Serial Data Input when in SPI Master Mode and Serial Data Output when in SPI Slave Mode. Optionally it can be used as general purpose I/O controlled by DSP0. 8 MOSIM/DSP0_GPIO2 I/O SPI Master Output Slave Input Serial Data (Input/Output)/ General Purpose I/O (Input/Output). Serial Data Output when in SPI Master Mode and Serial Data Input when in SPI Slave Mode. Optionally it can be used as general purpose I/O controlled by DSP0. 9 SSM/DSP0_GPIO3 I SPI Slave Select (Input)/General Purpose I/O (Input/Output). If SPI is enabled, behaves as Slave Select line for SPI bus. Optionally it can be used as general purpose I/O controlled by DSP0. 10 SCKD/DSP0_GPIO4 I SPI Bit Clock (Input)/General Purpose I/O (Input/Output). SPI bit clock. Optionally it can be used as general purpose I/O controlled by DSP0. 11 MISOD/DSP0_GPIO5 I/O SPI Master Input Slave Output Serial Data (Input/Output)/ General Purpose I/O (Input/Output). Behaves as Serial Data Input when in SPI Master Mode and Serial Data Output when in SPI Slave Mode. Optionally it can be used as general purpose I/ O controlled by DSP0. 12 MISOD/DSP0_GPIO6 I/O SPI Master Output Slave Input Serial Data (Input/Output)/ General Purpose I/O (Input/Output). Serial Data Output when in SPI Master Mode and Serial Data Input when in SPI Slave Mode. Optionally it can be used as general purpose I/O controlled by DSP0. 13 SSD/DSP0_GPIO7 I SPI Slave Select (Input)/General Purpose I/O (Input/Output). Behaves as Slave Select line for SPI bus. Optionally it can be used as general purpose I/O controlled by DSP0. |
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