Aug.2007

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Low Voltage Reset Circuit ( or Power Failed Detector ) 2.4V

The EU101x is built in Low-Voltage-Reset circuit to detect and against power noise. The low voltage

reset will be active when Vdd is dropped lower than 2.4V. Note that, in STOP mode, low voltage reset

function will be disabled by hardware. The low voltage reset function will be active when CPU is not

working in STOP mode.

HALT mode

counter. All the internal circuit will suspend, except system clock and timer/counter kept running. HALT

mode could be released from timer underflow or PB ports input signal from high to low. When halt mode

is released, program counter will execute next instruction after “STA $0EH”. If timer interrupt is enabled,

it serves timer interrupt first, and then execute next instruction after “STA $0EH”. When HALT mode is

released by PB ports falling-edge, program counter execute next instruction. If PB interrupt is enabled,

PBINT =1, PB interrupt subroutine will be activated.

Address

0EH

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

Name

HALT

#

#

#

#

#

#

#

#

STOP mode

When executed “STA $0FH”, whole chip will enter stop mode. The data in ACC could be any data of

#00H~#FFH. In stop mode, system clock and timer/counter will be stopped. At this condition, operating

current could be down less than 1µA. Only input signal from high to low of PB ports can release the chip

from STOP mode. When STOP mode is released by PB/PD ports, program counter will execute next

instruction of “STA $0FH”. If PB interrupt is enabled, PBINT=1, PB interrupt subroutine will be activated

first.

Address

0FH

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

Name

STOP

#

#

#

#

#

#

#

#

MCU system clock

This CPU is built-in internal RC oscillator whose frequency is 4MHz. The tolerance of the frequency is

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