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EM6156K1600TBA-55IF Scheda tecnica(PDF) 4 Page - Eorex Corporation

Il numero della parte EM6156K1600TBA-55IF
Spiegazioni elettronici  256Kx16 LP SRAM
PDF  12 Pages
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Produttore elettronici  EOREX [Eorex Corporation]
Homepage  http://www.eorex.com
Logo EOREX - Eorex Corporation

EM6156K1600TBA-55IF Scheda tecnica(HTML) 4 Page - Eorex Corporation

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256Kx16 LP SRAM EM6156K600V Series
4
DCC-SR-041003-A
-L
-
20
80
µA
Supply Current
ISB1
CE# V ≧ VCC - 0.2V
-LL
2
15
µA
Notes:
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.
3. Over/Undershoot specifications are characterized, not 100% tested.
4. 10µA for special request
5. Typical values are included for reference only and are not guaranteed or tested.
Typical valued are measured at VCC = VCC(TYP.) and TA = 25°C
CAPACITANCE (TA = 25°C , f = 1.0MHz)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
Input Capacitance
CIN
-
6
pF
Input/Output Capacitance
CI/O
-
8
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
0.2V to VCC - 0.2V
Input Rise and Fall Times
3ns
Input and Output Timing Reference Levels
1.5V
Output Load
CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA
AC ELECTRICAL CHARACTERISTICS
READ CYCLE
-45
-55
70
PARAMETER
SYM.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
UNIT
Read Cycle Time
tRC
45
-
55
-
70
-
ns
Address Access Time
tAA
-
45
-
55
-
70
ns
Chip Enable Access Time
tACE
-
45
-
55
-
70
ns
Output Enable Access Time
tOE
-
25
-
30
-
35
ns
Chip Enable to Output in Low-Z
tCLZ*
10
-
10
-
10
-
ns
Output Enable to Output in Low-Z
tOLZ*
5
-
5
-
5
-
ns
Chip Disable to Output in High-Z
tCHZ*
-
15
-
20
-
25
ns
Output Disable to Output in High-Z
tOHZ*
-
15
-
20
-
25
ns
Output Hold from Address Change
tOH
10
-
10
-
10
-
ns
LB#, UB# Access Time
tBA
-
45
-
55
-
70
ns
LB#, UB# to High-Z Output
tBHZ*
-
20
-
25
-
30
ns
LB#, UB# to Low-Z Output
tBLZ*
10
-
10
-
10
-
ns
WRITE CYCLE
-45
-55
70
PARAMETER
SYM.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
UNIT
Write Cycle Time
tWC
45
-
55
-
70
-
ns
Address Valid to End of Write
tAW
40
-
50
-
60
-
ns
Chip Enable to End of Write
tCW
40
-
50
-
60
-
ns
Address Set-up Time
tAS
0
-
0
-
0
-
ns
Write Pulse Width
tWP
35
-
45
-
55
-
ns
Write Recovery Time
twr
0
-
0
-
0
-
ns
Data to Write Time Overlap
tDW
20
-
25
-
30
-
ns
Data Hold from End of Write Time
tDH
0
-
0
-
0
-
ns
Output Active from End of Write
tOW*
5
-
5
-
5
-
ns
Write to Output in High-Z
tWHZ*
-
15
-
20
-
25
ns
LB#, UB# Valid to End of Write
tBW
35
-
45
-
60
-
ns
*These parameters are guaranteed by device characterization, but not production tested.



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