APM32E103RET6-R datasheet(41/79 Pages) GEEHY

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Symbol

Parameter

Conditions

Minimum

value

Typical

value

Maximum

value

Unit

voltage level

selection

PLS[2:0]=001 (falling edge)

2.16

2.19

PLS[2:0]=001(PVD hysteresis)

110

120

PLS[2:0]=010 (rising edgeg)

2.37

2.40

PLS[2:0]=010 (falling edge)

2.26

2.29

PLS[2:0]=010(PVD hysteresis)

100

110

PLS[2:0]=011 (rising edgeg)

2.46

2.50

PLS[2:0]=011 (falling edge)

2.36

2.39

PLS[2:0]=011(PVD hysteresis)

100

110

PLS[2:0]=100 (rising edgeg)

2.57

2.60

PLS[2:0]=100 (falling edge)

2.45

2.49

PLS[2:0]=100(PVD hysteresis)

110

120

PLS[2:0]=101 (rising edgeg)

2.66

2.70

PLS[2:0]=101 (falling edge)

2.56

2.59

PLS[2:0]=101(PVD hysteresis)

100

110

PLS[2:0]=110 (rising edgeg)

2.76

2.80

PLS[2:0]=110 (falling edge)

2.65

2.69

PLS[2:0]=110(PVD hysteresis)

110

PLS[2:0]=111 (rising edgeg)

2.87

2.91

PLS[2:0]=111 (falling edge)

2.75

2.79

PLS[2:0]=111(PVD hysteresis)

110

120

Note: It is obtained from a comprehensive evaluation and is not tested in production.

5.7.

Power consumption

Forms containing SDRAM are applicable to APM32E103xCxETxS, otherwise applicable to

APM32E103xCxETx.

5.7.1.

Power consumption test environment

（1） The values are measured by executing Dhrystone 2.1, with the Keil.V5 compilation

environment and the L0 compilation optimization level.

（2） All I/O pins are in input mode with a static value at VDD or VSS (no load)

（3） Unless otherwise specified, all peripherals are turned off

（4） The relationship between Flash waiting cycle setting and fHCLK :

0~24MHz: 0 waiting cycle

24~48MHz: 1 waiting cycle

48~72MHz: 2 waiting cycles

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