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IP2004 Scheda tecnica(PDF) 3 Page - International Rectifier |
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IP2004 Scheda tecnica(HTML) 3 Page - International Rectifier |
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3 / 15 page ![]() Page 3 of 15 www.irf.com 12/22/2007 Data Sheet No. PD60322 iP2004 PARAMETER Min Typ Max Units Conditions VDD Supply Current (Stand By) - 1.1 2.0 mA VDD = 5.0V, ENABLE = 0V Supply Current (Operating) - 70 110 mA VIN = 12V, VDD= EN ABLE = 5.0V, FSW = 1MHz, 10% DC, Power-On Reset (POR) VCC Rising 3.7 - 4.5 V Hysterisis 140 185 230 mV VI Rising & Falling ENABLE INPUT Logic Level Low Threshold (VIL) - - 0.8 V Schmitt Trigger Input VCC = POR to 6.0V Logic Level High Threshold (VIH) 2.0 - - V Threshold Hysterisis - 100 - mV Weak pull-down current - 10 - µA Rising Propagation Delay (TPDH) - 40 - ns Falling Propagation Delay (TPDL) - 75 - ns PWM INPUT Logic Level Low Threshold (VIL) - - 0.8 V Schmitt Trigger Input VCC = POR to 6.0V (Note 4) Logic Level High Threshold (VIH) 2.0 - - V Threshold Hysterisis - 100 - mV Weak pull-down current - 2 - µA Rising Propagation Delay (TPDH) - 50 - ns Falling Propagation Delay (TPDL) - 35 - ns Notes: 1. Must not exceed 6.5V. 2. Guaranteed by design, not tested in production. 3. Measurement made with six 10µF (TDK C3225X5R1C106KT or equivalent) ceramic capacitors across VIN to PGND pins (see Figure 9). 4. TPDH and TPDL are not associated with rise and fall times. Does not affect Power Loss (see Figure 10). 5. Block Temperature is defined as any Die temperature within the package. |
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