INA151CDDFR datasheet(26/39 Pages) TI2

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whereas:

• tacq, acquisition time of the ADC

• Vdroop, voltage droop caused by the change in charge on Cfilt during sampling, typically 100mV

• N, resolution of ADC

The nominal filter resistance can then be derived from:

Rfilt= τRCCfilt

(5)

For the given example of a 12-Bit system, with tacq=1μs, and a voltage droop of 100mV select Rfilt = 1.2kΩ.

The aforementioned series resistance equation is predicated on a predetermined ADC acquisition time

parameter, operating under the assumption that the output amplifier stage in the INA151 provides sufficient

driving capability to maintain fast settling during the ADC sampling phase.

The minimum achievable acquisition time that the INA151 can reliably support is dependent on the variant,

as each variant implements a different gain network and changes the available bandwidth of the output stage

(BW151), see Electrical Characteristics for each variant.

Use following equation to calculate the minimum acquisition time to drive with INA151:

tacq= 12π×BW151× 17×ln 0.5×FSR2N

Vdroop

(6)

8.2.1.2.3 ADC Input Protection

When the enable pin is driven to logic low (EN=LOW), the input amplifier stage is powered down to reduce the

input current to <1μA at no differential signal. The output stage is set to Hi-Z whereas the impedance is solely

determined by the internal resistor configuration R3+R2.

–

REF

VOUT

VCM

VS+

VCM

VDIFF

Max. ±5V

DGND

VS+

VSub

500k

62.5k

Variant A (G=1): 500k

Variant B (G=2/3): 333.33k

Variant C (G=½ ): 250k

Variant D (G=¼): 125k

Figure 8-3. INA151 Block Diagram

Note that the disabled output impedances are internally referenced to the negative supply, V−. When the device

is disabled and connected to a ground-referenced ADC input, voltage transients below ground potential can

INA151

SLVSIL6C – JANUARY 2026 – REVISED APRIL 2026

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