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STM32F101T4 Scheda tecnica(PDF) 69 Page - STMicroelectronics |
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STM32F101T4 Scheda tecnica(HTML) 69 Page - STMicroelectronics |
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69 / 87 page ![]() DocID15058 Rev 6 69/87 STM32F101x4, STM32F101x6 Electrical characteristics 86 Figure 33. Typical connection diagram using the ADC 1. Refer to Table 41 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 34. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 34. Power supply and reference decoupling ai14139d STM32F10xxx VDD AINx IL±1 µA 0.6 V VT RAIN(1) Cparasitic VAIN 0.6 V VT RADC(1) CADC(1) 12-bit converter Sample and hold ADC converter VDDA STM32F10xx4/6 1 µF // 10 nF VSSA ai15498 |
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