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M36DR232 Scheda tecnica(PDF) 6 Page - STMicroelectronics |
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M36DR232 Scheda tecnica(HTML) 6 Page - STMicroelectronics |
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6 / 46 page ![]() M36D232A, M36DR232B 6/46 Table 3. Main Operation Modes Note: X = VIL or VIH,VPPFH =12V ± 5%. 1. If UBS and LBS are tied together the bus is at 16 bit. For an 8 bit bus configuration use UBS and LBS separately. Operation Mode EF GF WF RPF WPF VPPF E1S E2S GS WS UBS,LBS (1) DQ15-DQ0 Read VIL VIL VIH VIH X Don't care SRAM must be disabled Data Output Write VIL VIH VIL VIH VIH VCCF or VPPFH SRAM must be disabled Data Input Block Locking VIL XX VIH VIL Don't care SRAM must be disabled X Standby VIH XX VIH X Don't care Any SRAM mode is allowable Hi-Z Reset X X X VIL X Don't care Any SRAM mode is allowable Hi-Z Output Disable VIL VIH VIH VIH X Don't care Any SRAM mode is allowable Hi-Z Read Flash must be disabled VIL VIH VIL VIH VIL Data out Word Read Write Flash must be disabled VIL VIH VIH VIL VIL Data in Word Write Standby/ Power Down Any Flash mode is allowable VIH XXX X Hi-Z X VIL X X X Hi-Z XXXX VIH Hi-Z Data Retention Any Flash mode is allowable VIH XXX X Hi-Z X VIL X X X Hi-Z XXXX VIH Hi-Z Output Disable Any Flash mode is allowable VIL VIH VIH VIH X Hi-Z |
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