M41T56

Operation

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2.3

WRITE mode

In this mode the master transmitter transmits to the M41T56 slave receiver. Bus protocol is

shown in Figure 11 on page 13. Following the START condition and slave address, a logic '0'

will follow and is to be written to the on-chip address pointer. The data word to be written to

the memory is strobed in next and the internal address pointer is incremented to the next

memory location within the RAM on the reception of an acknowledge clock. The M41T56

slave receiver will send an acknowledge clock to the master transmitter after it has received

the slave address and again after it has received the word address and each data byte (see

Figure 8 on page 12).

2.4

Data retention mode

WRITE cycles. Should the supply voltage decay, the M41T56 will automatically deselect,

accomplished by internally inhibiting access to the clock registers and SRAM.

battery supply.

For a further more detailed review of battery lifetime calculations, please see Application

Note AN1012.

Figure 11.

WRITE mode sequence

AI00591

BUS ACTIVITY:

S

P

SDA LINE

BUS ACTIVITY:

MASTER

DATA n

DATA n+1

DATA n+X

WORD

ADDRESS (n)

SLAVE

ADDRESS