854054AG

www.icst.com/products/hiperclocks.html

REV. A MARCH 29, 2006

7

Integrated

Circuit

Systems, Inc.

ICS854054

4:1

Figure 1 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = V

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and V

and R2/R1 = 0.609.

VDD

R2

1K

V_REF

C1

0.1u

R1

1K

Single Ended Clock Input

PCLK

nPCLK

For applications not requiring the use of a differential input, both

the PCLK and nPCLK pins can be left floating. Though not

required, but for additional protection, a 1k

Ω resister can be tied

from PCLK to ground.

All select pins have internal pull-ups and pull-downs;

additional resistance is not required but can be added for

additional protection. A 1k

Ω resister can be used.