APM32F103TBU6-R datasheet(39/78 Pages) GEEHY

39 / 78 page

w w w. g e e h y. c o m

P a g e 38

Parameter

Condition

fHCLK

Typical value (1)

Maximum value (1)

TA=25℃，VDD=3.3V

TA=105℃，VDD=3.6V

IDDA

(μA)

IDD (mA）

IDDA

(μA)

IDD (mA)

48MHz

96.67

10.45

119.9

14.42

36MHz

73.502

8.02

93.38

11.25

24MHz

54.12

5.61

72.03

8.06

16MHz

43.17

3.98

59.51

6.01

8MHz

2.65

2.28

12.95

3.81

The data are obtained from a comprehensive evaluation and are not tested in production.

The external clock is 8MHz. When fHCLK > 8MHz, the PLL is enabled.

5.7.3

Power consumption in sleep mode

Table27 Power consumption of code running in Flash or RAM in sleep mode

Parameter

Condition

fHCLK

Typical value (1)

Maximum value (1)

TA=25℃，VDD=3.3V

TA=105℃，VDD=3.6V

IDDA

(μA)

IDD (mA）

IDDA

(μA)

IDD (mA)

Power

consumption in

sleep mode

External clock (2), enabling all

peripherals

96 MHz

205.89

18.77

242.73

20.99

72MHz

130.77

12.92

153.78

14.38

48MHz

96.77

9.93

114.87

10.97

36MHz

73.42

7.68

89.42

9.69

24MHz

53.85

5.36

68.74

6.14

16MHz

42.64

3.83

57.25

4.57

8MHz

2.65

2.12

5.7

2.84

External clock (2), disabling all

peripherals

96 MHz

205.62

7.13

242.64

8.17

72MHz

130.66

5.02

153.71

5.91

48MHz

96.68

3.95

114.84

4.76

36MHz

73.36

3.14

89.36

3.89

24MHz

53.82

2.34

68.73

3.08

16MHz

42.61

1.8

57.25

2.52

8MHz

2.65

1.16

5.71

1.83

The data are obtained from a comprehensive evaluation and are not tested in production.

The external clock is 8MHz. When fHCLK > 8MHz, the PLL is enabled.

APM32F103TBU6-R Scheda tecnica(PDF) 39 Page - Geehy Semiconductor Co., Ltd.

APM32F103TBU6-R Scheda tecnica(HTML) 39 Page - Geehy Semiconductor Co., Ltd.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

Scheda tecnica Scarica

Link URL