TMS320VC5502 datasheet(64/190 Pages) TI

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166J – APRIL 2001 – REVISED AUGUST 2006

3.10.5.6 PLL Divider3 Register (PLLDIV3) for SYSCLK3

This register controls the value of the divider D3 for SYSCLK3. It is in both the BYPASS and PLL paths.

D3EN

Reserved

R/W, 1

R, 0000000

Reserved

PLLDIV3

R, 000

R/W, 00011

LEGEND: R = Read, W = Write, n = value at reset

Figure 3-20. PLL Divider 3 Register Layout (0x1C90)

Table 3-18. PLL Divider 3 Register Bit Field Description

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

D3EN

R/W

Divider D3 enable

•

D3EN = 0: Divider 3 disabled

•

D3EN = 1: Divider 3 enabled

Reserved

14:5

0000000000

Reserved. Reads return 0. Writes have no effect.

PLLDIV3

4:0

R/W

00011

Divider D3 ratio (SYSCLK3 divider)

•

PLLDIV3 = 00000: Divide by 1

•

PLLDIV3 = 00001: Divide by 2

•

PLLDIV3 = 00010: Reserved

•

PLLDIV3 = 00011: Divide by 4

•

PLLDIV3 = 00100–11111: Reserved

3.10.5.7 Oscillator Divider1 Register (OSCDIV1) for CLKOUT3

This register controls the value of the divider OD1 for CLKOUT3. It does not go through the PLL path.

OD1EN

Reserved

R/W, 0

R, 0000000

Reserved

OSCDIV1

R, 000

R/W, 00000

LEGEND: R = Read, W = Write, n = value at reset

Figure 3-21. Oscillator Divider1 Register Layout (0x1C92)

Functional Overview

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