DIO2186

Version 1.0, Apr 2026

www.dioo.com

© 2026 Dioo Microcircuits Co., Ltd. Jiangsu

9

REF

Shunt

LOAD

OUT

V

+

Gain)

×

R

×

(I

=

V

(1)

Where,

ILOAD is the load current to be monitored.

RShunt is the current-sense resistor.

Gain is the gain option of the selected device.

VREF is the voltage applied to the REF pin.

8.5. High-side and low-side current sensing

The DIO2186 supports input common-mode voltages from -2 V to 40 V. Its internal topology ensures that

the common-mode range is not limited by the power-supply voltage VS. This enables the DIO2186 to

operate with common-mode voltages both exceeding and falling below VS. The figure below is the typical

application of the DIO2186 in high-side and low-side current sensing.

Figure 9. High-side and Low-side sensing connections

8.6. High common-mode rejection

The DIO2186 employs a capacitively coupled amplifier at the input stage, which blocks DC common-mode

voltages from reaching downstream circuits, resulting in very high common-mode rejection (about 150 dB

typically). This capability to reject changes in DC common-mode voltage allows the device to measure

currents on both high- and low-voltage rails with minimal offset.

8.7. Rail-to-rail output swing

The DIO2186 supports linear current-sensing operation with its output voltage capable of swinging close to

both the supply rail and ground. The maximum output swing towards the positive rail is specified as VS - 40

mV, while the maximum output swing near ground is limited to GND + 1 mV. This near-rail output swing

capability is particularly beneficial for maximizing the effective output range, especially when the device is

powered from a 2.5 V supply.

8.8. Device functional modes

8.8.1. Normal operation

The DIO2186 operates under normal conditions when all the following criteria are satisfied:



The power-supply voltage (VS) must be within the range of 2.5 V to 6 V.



The common-mode voltage (VCM) must be within the specified range of -2 V to 40 V.



The maximum differential input voltage times the gain plus VREF, must remain below the positive output

swing limit VSP.



The minimum differential input signal multiplied by the gain, added to VREF, must exceed the zero load