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M68AW064FZB Scheda tecnica(PDF) 8 Page - STMicroelectronics

Il numero della parte M68AW064FZB
Spiegazioni elettronici  1 Mbit 64K x16 3.0V Asynchronous SRAM
PDF  18 Pages
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Produttore elettronici  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M68AW064FZB Scheda tecnica(HTML) 8 Page - STMicroelectronics

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M68AW064F
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OPERATION
The M68AW064F has a Chip Enable power down
feature which invokes an automatic standby mode
whenever either Chip Enable is de-asserted
(E = High) or LB and UB are de-asserted (LB and
UB = High). An Output Enable (G) signal provides
a high speed tri-state control, allowing fast read/
write cycles to be achieved with the common I/O
data bus. Operational modes are determined by
device control inputs W, E, LB and UB as summa-
rized in the Operating Modes table (see Table 6).
Table 6. Operating Modes
Note: 1. X = VIH or VIL.
Read Mode
The M68AW064F is in the Read mode whenever
Write Enable (W) is High with Output Enable (G)
Low, and Chip Enable (E) is asserted. This pro-
vides access to data from eight or sixteen, de-
pending on the status of the signal UB and LB, of
the 1,048,576 locations in the static memory array,
specified by the 16 address inputs. Valid data will
be available at the eight or sixteen output pins
within tAVQV after the last stable address, provid-
ing G is Low and E is Low. If Chip Enable or Output
Enable access times are not met, data access will
be measured from the limiting parameter (tELQV,
tGLQV or tBLQV) rather than the address. Data out
may be indeterminate at tELQX, tGLQX and tBLQX
but data lines will always be valid at tAVQV.
Figure 7. Address Controlled, Read Mode AC Waveforms
Note: E = Low, G = Low, W = High, UB = Low and/or LB = Low.
Operation
E
W
G
LB
UB
DQ0-DQ7
DQ8-DQ15
Power
Deselected/Power-down
VIH
XXXX
Hi-Z
Hi-Z
Standby (ISB)
Deselected/Power-down
X
X
X
VIH
VIH
Hi-Z
Hi-Z
Standby (ISB)
Lower Byte Read
VIL
VIH
VIL
VIL
VIH
Data Output
Hi-Z
Active (ICC)
Lower Byte Write
VIL
VIL
X
VIL
VIH
Data Input
Hi-Z
Active (ICC)
Output Disabled
VIL
X
VIH
VIL
X
Hi-Z
Hi-Z
Active (ICC)
Output Disabled
VIL
X
VIH
X
VIL
Hi-Z
Hi-Z
Active (ICC)
Upper Byte Read
VIL
VIH
VIL
VIH
VIL
Hi-Z
Data Output
Active (ICC)
Upper Byte Write
VIL
VIL
X
VIH
VIL
Hi-Z
Data Input
Active (ICC)
Word Read
VIL
VIH
VIL
VIL
VIL
Data Output
Data Output
Active (ICC)
Word Write
VIL
VIL
X
VIL
VIL
Data Input
Data Input
Active (ICC)
AI04876
tAVAV
tAVQV
tAXQX
A0-A15
DQ0-DQ15
VALID
DATA VALID



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