M7010R datasheet(15/67 Pages) STMICROELECTRONICS

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M7010R

Table 7. AC Timing Parameters with CLK2X

Note: 1. Valid for Ambient Operating Temperature: TA =0to70°C; VDD =1.8V.

2. Values are based on 50% signal levels.

3. BasedonanAC load of CL=50pF (seeFigure5, page12and Figure 8, page 12).

4. Unless otherwise noted, all values are based on AC load of CL = 50pF (see Figure 5, page 12 and Figure 8, page 12).

5. These parameters are sampled and not 100% tested.

Row

Symbol

M7010R-066

M7010R-083

Unit

Description(1)

Min

Max

Min

Max

fCLK

133

166

MHz CLK2X frequency

tCLK

7.5

6.0

CLK2X period

tCKHI

3.0

2.4

CLK2X high pulse(2)

tCKLO

3.0

2.4

CLK2X low pulse(2)

tISCH

2.5

1.8

Input Setup Time to CLK2X rising edge(2)

tIHCH

0.6

Input Hold Time to CLK2X rising edge(2)

tICSCH

4.2

3.5

Cascaded Input Setup Time to CLK2X rising edge(2)

tICHCH

0.6

Cascaded Input Hold Time to CLK2X rising edge(2)

tCKHOV

8.5

7.0

Rising edge of CLK2X to LHO, FULO, BHO, FULL valid(3)

tCKHDV

9.0

7.5

Rising edge of CLK2X to DQ valid(4)

tCKHDZ

8.5

7.0

Rising edge of CLK2X to DQ high-Z(5)

tCKHSV

9.0

7.5

Rising edge of CLK2X to SRAM Bus valid(4)

tCKHSHZ

6.5

6.0

Rising edge of CLK2X to SRAM Bus high-Z(4,5)

tCKHSLZ

7.0

6.5

Rising edge of CLK2X to SRAM Bus low-Z(4,5)

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