AS7211 datasheet(22/37 Pages) AMSOSRAM

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[v1-00] 2016-Dec-23

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AS7211 − Detailed Description

In order to change the data direction a repeated START

condition is issued on the 1st SCL pulse after the acknowledge

bit of the word address transfer. After the reception of the

device-read address, the slave becomes the transmitter. In this

state the slave transmits register data located by the previous

received word address vector. The master responds to the data

byte with a not-acknowledge, and issues a STOP condition on

the bus.

Figure 26:

I²C Sequential Read

I²C Sequential Read: Shows the format of an I²C sequential read access.

Sequential Read is the extended form of Random Read, as more

than one register-data bytes are transferred subsequently. In

difference to the Random Read, for a sequential read the

transferred register-data bytes are responded by an

acknowledgement from the master. The number of data bytes

transferred in one sequence is unlimited (consider the behavior

of the word-address counter). To terminate the transmission the

master has to send a not-acknowledge following the last data

byte and generate the STOP condition subsequently.

The AS7211 is compatible to the NXP two wire specifications.

http://www.nxp.com/documents/user_manual/UM10204.pdf

Version 4.0 Feb 2012 for standard mode and fast mode.

Data 1

N P

WA++

read WA++

Data n

read WA++

AS7211 Scheda tecnica(PDF) 22 Page - ams-OSRAM AG