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Table 2.46

Option setting memory characteristics (2 of 2)

Conditions: Program: FCLK = 4 to 50 MHz

Read: FCLK ≤ 50 MHz

Parameter

Symbol

FCLK = 4 MHz

20 MHz ≤ FCLK ≤ 50 MHz

Unit

Test conditions

Min

Typ*4

Max

Min

Typ*4

Max

Data hold time*2

tDRP

10*2 *3

—

10*2 *3

—

Years

30*2 *3

—

30*2 *3

—

Ta = +85°C

Note 1. This is the minimum number of times to guarantee all the characteristics after reprogramming. The guaranteed range is from 1 to

the minimum value.

Note 2. This indicates the minimum value of the characteristic when reprogramming is performed within the specified range.

Note 3. This result is obtained from reliability testing.

Note 4. The reference value at VCC = 3.3 V and room temperature.

2.12

Serial Wire Debug (SWD)

Table 2.47

SWD

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

SWCLK clock cycle time

tSWCKcyc

—

Figure 2.60

SWCLK clock high pulse width

tSWCKH

—

SWCLK clock low pulse width

tSWCKL

—

SWCLK clock rise time

tSWCKr

—

SWCLK clock fall time

tSWCKf

—

SWDIO setup time

tSWDS

—

Figure 2.61

SWDIO hold time

tSWDH

—

SWDIO data delay time

tSWDD

—

SWCLK

tSWCKH

tSWCKcyc

tSWCKL

Figure 2.60

SWD SWCLK timing

RA4T1 Datasheet

2. Electrical Characteristics

R01DS0415EJ0140 Rev.1.40

May 29, 2026

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