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AS1163

Functional description

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6.8

I²C bridge

The device can operate as an OSP-to-I²C-gateway as illustrated in the Figure 21, using one

LED channel for the I²C pads.

Figure 21: OSP-to-I²C bridge

Note: In an I²C read transaction, the AS1163 does not generate the clock pulse for the last

ack/nack.

6.8.1

I²C bridge configuration

If the OTP bit I2C_BRIDGE_EN is high, channel 2 is configured as I²C bridge.

A dedicated de-glitch filter provides protection against glitches with nominal duration < 50 ns,

complying with the I²C standard.

Specifically, the drivers belonging to channel 2 are re-purposed to serve as I²C-compatible

interface (R2, G2, B2 become SDA, SCL and INT) as shown in Table 2 and Table 3 external

pull-up resistors to VDD are required: The value of the pull-ups depends on system design,

see “I²C-bus specification and user manual” UM10204 section 7.1 for details. A typical value is

4.7kOhm.

The third driver of the channel is permanently OFF and working as digital input for the interrupt

bit, which is active low. The interrupt flag is stored into the I²C register and is available to the

customer for reading (see READI2CCFG).

Table 12: Channel 2 configuration when I²C bridge is enabled

I²C function

SDA

SCL

INTERRUPT

Driver enable state (direction)

Input/output

Output

Input

Interrupt is captured by the digital part via a dedicated register.

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