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[v1-05] 2019-Feb-15

AS3953A − Detailed Description

ISO 14443A Level-3 Protocol Mode

Level-3 Protocol mode is intended for implementation of

custom protocols for which coding on Level-4 of ISO 14443A

communication according to Figure 34 is not appropriate. In

this mode Level-2 and Level-3 behavior of the PICC logic is

identical to ISO 14443A Level-4 Protocol mode, while on Level-4

all received data blocks are put in FIFO.

In case the configuration bit irq_l4 is set an interrupt is

automatically sent to controller once the PICC Logic enters in

ACTIVE(*) state (after sending SAK on Cascade Level 2).

In this mode the EEPROM can be accessed via SPI when the RF

field is active.

Transparent Mode

In the Transparent Mode the AS3953A logic is bypassed, AFE

input and output signals are directly available on SPI interface

pins when /SS signal is high.

• Modulator switch is controlled by pin MOSI (high is

modulator on)

• Clock extractor output is sent to pin MISO

• Demodulator output is sent to pin IRQ

When /SS signal is low the SPI interface pins resume its normal

functionality.

In this mode the EEPROM can be accessed via SPI when the RF

field is active.

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