M74HCT74

2/10

INPUT AND OUTPUT EQUIVALENT CIRCUIT

PIN DESCRIPTION

TRUTH TABLE

X : Don’t Care

LOGIC DIAGRAM

This logic diagram has not be used to estimate propagation delays

PIN No

SYMBOL

NAME AND FUNCTION

1,13

1CLR, 2CLR

Asynchronous Reset -

Direct Input

2, 12

1D, 2D

Data Inputs

3, 11

1CK, 2CK

Clock Input

(LOW-to-HIGH,

Edge-Triggered)

4, 10

1PR, 2PR

Asynchronous Set - Direct

Input

5, 9

1Q, 2Q

True Flip-Flop Outputs

6, 8

1Q, 2Q

Complement Flip-Flop

Outputs

7

GND

Ground (0V)

14

Vcc

Positive Supply Voltage

INPUTS

OUTPUTS

FUNCTION

CLR

PR

DCK

Q

Q

L

H

X

X

L

H

CLEAR

H

L

X

X

H

L

PRESET

L

L

X

X

H

H

----

H

H

L

L

H

----

H

H

H

H

L

----

HH

X

NO CHANGE