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R5F564MJGDFC Scheda tecnica(PDF) 78 Page - Renesas Technology Corp |
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R5F564MJGDFC Scheda tecnica(HTML) 78 Page - Renesas Technology Corp |
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78 / 162 page ![]() R01DS0173EJ0120 Rev.1.20 Page 78 of 162 Oct 20, 2022 RX64M Group 2. Electrical Characteristics Figure 2.6 LOCO Clock Oscillation Start Timing Figure 2.7 IWDT-dedicated Low-Speed Clock Oscillation Start Timing Table 2.16 LOCO and IWDT-Dedicated Low-Speed Clock Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0, VCC_USBA = AVCC_USBA = 3.0 to 3.6 V, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V, Ta = Topr Item Symbol Min. Typ. Max. Unit Test Conditions LOCO clock cycle time tLcyc 3.78 4.16 4.63 µs LOCO clock oscillation frequency fLOCO 216 240 264 kHz LOCO clock oscillation stabilization wait time tLOCOWT — — 44 µs Figure 2.6 IWDT-dedicated low-speed clock cycle time tILcyc 7.57 8.33 9.26 µs IWDT-dedicated low-speed clock oscillation frequency fILOCO 108 120 132 kHz IWDT-dedicated low-speed clock oscillation stabilization wait time tILOCOWT — 142 190 µs Figure 2.7 LOCO clock LOCOCR.LCSTP tLOCOWT On-chip oscillator output OSCOVFSR.ILCOVF ILOCOCR.ILCSTP tILOCOWT IWDT-dedicated low-speed clock IWDT-dedicated on-chip oscillator output |
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