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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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R5F564MJGDFC Scheda tecnica(PDF) 108 Page - Renesas Technology Corp |
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R5F564MJGDFC Scheda tecnica(HTML) 108 Page - Renesas Technology Corp |
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108 / 162 page  R01DS0173EJ0120 Rev.1.20 Page 108 of 162 Oct 20, 2022 RX64M Group 2. Electrical Characteristics 2.3.7.8 SCI Note 1. tPBcyc: PCLKB cycle; tPAcyc: PCLKA cycle Note 2. When the SEMR.ABCS and SEMR.BGDM bits are set to 1 Note 3. When the SEMR.ABCS0 and SEMR.BGDM bits are set to 1 Table 2.32 SCI and SCIF Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0, VCC_USBA = AVCC_USBA = 3.0 to 3.6 V, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF High-drive output is selected by the driving ability control register. Item Symbol Min.*1 Max.*1 Unit*1 Test Conditions SCI Input clock cycle Asynchronous tScyc 4 — tPBcyc Figure 2.47 Clock synchronous 6— Input clock pulse width tSCKW 0.4 0.6 tScyc Input clock rise time tSCKr —5 ns Input clock fall time tSCKf —5 ns Output clock cycle Asynchronous*2 tScyc 8— tPBcyc Clock synchronous 4— Output clock pulse width tSCKW 0.4 0.6 tScyc Output clock rise time tSCKr —5 ns Output clock fall time tSCKf —5 ns Transmit data delay time Clock synchronous tTXD — 28 ns Figure 2.48 Receive data setup time Clock synchronous tRXS 15 — ns Receive data hold time Clock synchronous tRXH 5— ns SCIF Input clock cycle Asynchronous tScyc 4— tPAcyc Figure 2.47 Clock synchronous 12 — Input clock pulse width tSCKW 0.4 0.6 tScyc Input clock rise time tSCKr —5 ns Input clock fall time tSCKf —5 ns Output clock cycle Asynchronous*3 tScyc 8— tPAcyc Clock synchronous 4— Output clock pulse width tSCKW 0.4 0.6 tScyc Output clock rise time tSCKr —5 ns Output clock fall time tSCKf —5 ns Transmit data delay time Master tTXD — 10 ns Figure 2.48 Slave — 4 × tPAcyc + 20 Receive data setup time Master tRXS 3 × tPAcyc + 20 — ns Slave tPAcyc + 10 — Receive data hold time Master tRXH –3 × tPAcyc + 5 — ns Slave 2 × tPAcyc + 10 — |
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