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ADSP-21990BBC Scheda tecnica(PDF) 1 Page - Analog Devices |
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ADSP-21990BBC Scheda tecnica(HTML) 1 Page - Analog Devices |
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1 / 50 page  a Mixed-Signal DSP Controller ADSP-21990 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. FEATURES ADSP-2199x, 16-bit, fixed-point DSP core with up to 160 MIPS sustained performance 8K words of on-chip RAM, configured as 4K words on-chip, 24-bit program RAM and 4K words on-chip, 16-bit data RAM External memory interface Dedicated memory DMA controller for data/instruction transfer between internal/external memory Programmable PLL and flexible clock generation circuitry enables full speed operation from low speed input clocks IEEE JTAG Standard 1149.1 test access port supports on-chip emulation and system debugging 8-channel, 14-bit analog-to-digital converter system, with up to 20 MSPS sampling rate (at 160 MHz core clock rate) 3-phase, 16-bit, center-based PWM generation unit with 12.5 ns resolution at 160 MHz core clock (CCLK) rate Dedicated 32-bit encoder interface unit with companion encoder event timer Dual 16-bit auxiliary PWM outputs 16 general-purpose flag I/O pins 3 programmable 32-bit interval timers SPI communications port with master or slave operation Synchronous serial communications port (SPORT) capable of software UART emulation Integrated watchdog timer Dedicated peripheral interrupt controller with software priority control Multiple boot modes Precision 1.0 V voltage reference Integrated power-on-reset (POR) generator Flexible power management with selectable power-down and idle modes 2.5 V internal operation with 3.3 V I/O Operating temperature range of –40 C to +85 C 196-ball CSP_BGA and 176-lead LQFP package Figure 1. Functional Block Diagram ADC CONTROL VREF PIPELINE FLASH ADC CLOCK GENERATOR/PLL PM ADDRESS/DATA DM ADDRESS/DATA I/O BUS 4k 16 DM RAM 4k 24 PM RAM EXTERNAL MEMORY INTERFACE (EMI) TIMER 0 TIMER 1 TIMER 2 4k 24 PM ROM ADSP-219x DSP CORE JTAG TEST AND EMULATION ADDRESS DATA CONTROL I/O REGISTERS PWM GENERATION UNIT ENCODER INTERFACE UNIT (AND EET) AUXILIARY PWM UNIT FLAG I/O SPI SPORT WATCHDOG TIMER INTERRUPT CONTROLLER (ICNTL) POR MEMORY DMA CONTROLLER |
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