R5F526TACDFM datasheet(97/142 Pages) RENESAS

97 / 142 page

R01DS0407EJ0120 Rev.1.20

Page 97 of 142

Oct 31, 2024

RX26T Group

2. Electrical Characteristics

Note 1. tPcyc refers to the period of PCLKB in RSCI8 and RSCI9, and of PCLKA in RSCI11.

Figure 2.47

Simple SPI Clock Timing

Table 2.36

Simple SPI Timing

Conditions: VCC = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5 V,

VSS = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the driving ability control register.

Item

Symbol

Min.

Max.

Unit*1

Test Conditions

Simple

SPI

SCK clock cycle output (master)

tSPcyc

2—

tPcyc

Figure 2.47

SCK clock cycle input (slave)

—

SCK clock high pulse width

tSPCKWH

0.4

0.6

tSPcyc

SCK clock low pulse width

tSPCKWL

0.4

0.6

tSPcyc

SCK clock rise/fall time

Output

tSPCKr, tSPCKf

—5

Input

—

µs

Data input setup time

Master

tSU

0.5

—

Figure 2.48 to Figure 2.51

Slave

2.5

—

Data input hold time

Master

—

Slave

2.5

—

Data output delay time

Master

tOD

—

Figure 2.48 to Figure 2.51

Slave

—

VCC ≥ 4.5V Figure 2.48 to

Figure 2.51

—

VCC < 4.5V

Data output hold time

Master

tOH

–1

—

Figure 2.48 to Figure 2.51

Slave

—

Data rise/fall time

Output

tDr, tDf

—5

Input

—

Slave access time

tSA

—5

tPcyc

Figure 2.50, Figure 2.51

Slave output release time

tREL

—5

tPcyc

SS input setup time

tLEAD

1—

tSPcyc

Figure 2.48 to Figure 2.51

SS input hold time

tLAG

1—

tSPcyc

SS input rise/fall time

tSSLr, tSSLf

—1

µs

tSPCKWH

VOH

VOL

VOH

tSPCKWL

tSPCKr

tSPCKf

VOL

tSPcyc

tSPCKWH

VIH

VIL

VIH

tSPCKWL

tSPCKr

tSPCKf

VIL

tSPcyc

VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC

(n = 008, 009, and 011)

SCKn output

(master)

SCKn input

(slave)

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