R5F56519FDFB datasheet(7/188 Pages) RENESAS

7 / 188 page

RX65N Group, RX651 Group

1. Overview

R01DS0276EJ0240 Rev.2.40

Page 7 of 188

Oct 31, 2023

Timers

8-bit timers (TMRb)

 (8 bits × 2 channels) × 2 units

 Select from among seven internal clock signals (PCLKB/1, PCLKB/2, PCLKB/8,

PCLKB/32, PCLKB/64, PCLKB/1024, PCLKB/8192) and one external clock signal

 Capable of output of pulse trains with desired duty cycles or of PWM signals

 The 2 channels of each unit can be cascaded to create a 16-bit timer

 Generation of triggers for A/D converter conversion

 Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12

 Event linking by the ELC

Compare match timer

(CMT)

 (16 bits × 2 channels) × 2 units

 Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128,

PCLKB/512)

 Event linking by the ELC

Compare match timer W

(CMTW)

 (32 bits × 1 channel) × 2 units

 Compare-match, input-capture input, and output-comparison output are available.

 Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128,

PCLKB/512)

 Interrupt requests can be output in response to compare-match, input-capture, and

output-comparison events.

 Event linking by the ELC

Realtime clock (RTCd)*4

 Clock sources: Main clock, sub clock

 Selection of the 32-bit binary count in time count/second unit possible

 Clock and calendar functions

 Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt

 Battery backup operation

 Time-capture facility for three values

 Event linking by the ELC

Watchdog timer (WDTA)

 14 bits × 1 channel

 Select from among 6 counter-input clock signals (PCLKB/4, PCLKB/64, PCLKB/128,

PCLKB/512, PCLKB/2048, PCLKB/8192)

Independent watchdog

timer (IWDTa)

 14 bits × 1 channel

 Counter-input clock: IWDT-dedicated on-chip oscillator

 Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64,

dedicated clock/128, dedicated clock/256

 Window function: The positions where the window starts and ends are specifiable (the

window defines the timing with which refreshing is enabled and disabled).

 Event linking by the ELC

Communication

function

Ethernet controller

(ETHERC)

 Input and output of Ethernet/IEEE 802.3 frames

 Transfer at 10 or 100 Mbps

 Full- and half-duplex modes

 MII (Media Independent Interface) or RMII (Reduced Media Independent Interface) as

defined in IEEE 802.3u

 Detection of Magic PacketsTM*1 or output of a “wake-on-LAN” signal (WOL)

 Compliance with flow control as defined in IEEE 802.3x standards

DMA controller for

Ethernet controller

(EDMACa)

 Alleviation of CPU load by the descriptor control method

 Transmission FIFO: 2 Kbytes; Reception FIFO: 2 Kbytes

USB 2.0 FS host/

function module (USBb)

 Includes a UDC (USB Device Controller) and transceiver for USB 2.0 FS

 One port

 Compliance with the USB 2.0 specification

 Transfer rate: Full speed (12 Mbps), low speed (1.5 Mbps) (host only)

 Both self-powered mode and bus-powered mode are supported

 OTG (On the Go) operation is possible (low-speed is not supported)

 Incorporates 2 Kbytes of RAM as a transfer buffer

 External pull-up and pull-down resistors are not required

Table 1.1

Outline of Specifications (6/10)

Classification

Module/Function

Description

R5F56519FDFB Scheda tecnica(PDF) 7 Page - Renesas Technology Corp

R5F56519FDFB Scheda tecnica(HTML) 7 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL