R5F5671CDDFB datasheet(141/179 Pages) RENESAS

141 / 179 page

R01DS0373EJ0120 Rev.1.20

Page 141 of 179

Sep 30, 2024

RX671 Group

2. Electrical Characteristics

2.4.7.13

RSPIA

Note 1. tPAcyc: PCLKA cycle

Note 2. When a letter “-A”, “-B”, etc. to indicate group membership is appended to the pin name, each pin is recommended to use in

combination with the pins in the same group. All RSPIA AC timings are measured in combination with the pins in the same

group.

Table 2.44

RSPIA Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-speed interface high-drive output is selected by the drive capacity control register.

Item

Symbol

Min.*1

Max.*1

Unit*1

Test

Conditions*2

RSPI

RSPCK clock cycle

Master

tSPcyc

2—

tPAcyc Figure 2.75

Slave

—

RSPCK clock high pulse width

Master

tSPCKWH

(tSPcyc – tSPCKr

– tSPCKf) / 2 – 3

—ns

Slave

0.4

0.6

tSPcyc

RSPCK clock low pulse width

Master

tSPCKWL

(tSPcyc – tSPCKr

– tSPCKf) / 2 – 3

—ns

Slave

0.4

0.6

tSPcyc

RSPCK clock rise/fall time

Output

tSPCKr,

tSPCKf

—5

Input

—

µs

Data input setup time

Master

tSU

—

Figure 2.76 to

Figure 2.82

Slave

2.5

—

Data input hold time

Master

5.7

—

Slave

2.5

—

SSL setup time

Master

tLEAD

tSPcyc

Slave

—

tPAcyc

SSL hold time

Master

tLAG

tSPcyc

Slave

—

tPAcyc

Data output delay time

Master

tOD

—4

Slave

—

Data output hold time

Master

tOH

0—

Slave

—

Successive transmission delay

time

Master

tTD

tSPcyc + 2 × tPAcyc

8 × tSPcyc

+ 2 × tPAcyc

Slave

tSPcyc

—

MOSI and MISO

rise/fall time

Output

tDr, tDf

—5

Input

—

µs

SSL

rise/fall time

Output

tSSLr,

tSSLf

—5

Input

—

µs

Slave access time

tSA

—

Figure 2.79,

Figure 2.80

Slave output release time

tREL

—20

TI SSP SS input setup time

Slave

tTISS

4.5

—

Figure 2.81,

Figure 2.82

TI SSP SS input hold time

Slave

tTISH

2.5

—

TI SSP next-access delay time

Slave

tTIND

2 × tPAcyc +

SLNDL × tPAcyc

—ns

TI SSP SS output delay time

Master

tTISSOD

—7

Figure 2.78

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