RZSLASHG2LC datasheet(71/74 Pages) RENESAS

71 / 74 page

RZ/G2L Group, RZ/G2LC Group

REVISION HISTORY

R01DS0484EJ0110

Rev.1.10

Page 71 of 74

May 30, 2025

REVISION HISTORY

RZ/G2L Group, RZ/G2LC Group DATASHEET

REVISION HISTORY

Description

Rev.

Date

Page

Summary

1.00

Dec 25, 2024



First edition issued

1.10

May 30, 2025 1. Overview

1.1.4 External Memory Interface

SPI Multi I/O Bus Controller: The description, modified (Note, added)

Figure 1.1 Configuration of LSI Internal Bus

Text, modified (MPU Bus

→ MCPU Bus)

SRC, deleted

Table 1.1 Product Lineup

Note 2, added

3. Electrical Characteristics

Table 3.3 DC Characteristics (1) [3.3-V I/O]

Input leakage current, added

Table 3.7 DC Characteristics (5) [RGMII/MII]

Input logic low (Remarks: 1.8-V RGMII/MII): The Min value, modified

Table 3.9 DC Characteristics (7) [1.8 V I/O (SD, QSPI)]

Output logic high voltage: The Min value, modified

Output logic low voltage: The Max value, modified

Table 3.18 DC Characteristics (16) [ADC]

Full-scale error, Offset error, Analog input capacitance, Analog input resistance, External

capacitance, and External resistance, added

Note 1, added

Figure 3.4 Analog Input Equivalent Circuit, added

Table 3.21 SDHC AC Access Timing (SDR at 3.3-V Operation)

SD_CLK clock high level width, SD_CLK clock low level width, SD_CMD,SD_DATA output

delay: The Min values, modified

Table 3.22 eMMC Host Interface Timing (MMC Default 3.3-V Power Supply)

SD0_CLK clock cycle, SD0_CLK clock high level width, SD0_CLK clock low level width,

SD0_CMD/SDDAT output delay: The Min values, modified

Table 3.23 eMMC Host Interface Timing (MMC Default 1.8-V Power Supply)

SD0_CLK clock cycle, SD0_CLK clock high level width, SD0_CLK clock low level width:

The Min values, modified

SD0_CMD/SDDAT output delay: The Min and Max values, modified

3.5.3.2 eMMC host interface timing (HS-SDR), modified

Table 3.26 eMMC Host Interface Timing (HS200 1.8-V Power Supply Operation, Output

Load 15 pF)

SD0_CLK clock high level width, SD0_CLK clock low level width: The Min values, modified

SD0_CMD/SDDAT output delay: The Min and Max values, modified

Table 3.34 Ethernet-IF Access Timing (Ether RGMII)

Duty cycle for gigabit: The Min and Max values, modified

Note, modified

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