MK50H28 datasheet(29/64 Pages) STMICROELECTRONICS

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BIT

NAME

DESCRIPTION

02:00

LBACK

Loopback Control puts MK50H28 into one of several loopback configurations.

LBACK

DESCRIPTION

Normal operation. No loopback.

Simple loopback. Receive data and clock are driven internally by

transmit data and clock. Transmit clock must be supplied externally

Clockless loopback. Receive data is driven internally by transmit data.

Transmit and receive clocks are driven by SYSCLK divided by 8.

Silent loopback. Same as simple loopback with td pin forced to all ones.

Silent clockless loopback. Combination of Silent and Clockless

loopbacks. Receive data is driven internally by transmit data, transmit

and receive clocks are driven by SYSCLK divided by 8. The TD pin is

forced to all ones.

4.2.2 Timers/Counters

There are 8 independent counter-timers. The lower 8 bits of IADR+08 are used as a scaler for nT1,

nT2 and TP. The scaler is driven by a clock which is 1/32 of SYSCLK. The dN1 is a 16 bit counter and

is used to count the number of bytes in a frame. The counters nN1, nN2, and nN3 are used for the LMI

frames. The Host will write the periods of all the timers/counters into the Initialization Block.

IADR + 08

SCALER

IADR + 10

TIMER nT1 / T391

IADR + 12

IADR + 14

TIMER TP

IADR + 06

COUNTER dN1

IADR + 04

User N393/nN3

COUNTER nN1 / N391

TIMER nT2 / T392

User N392/nN2

Ntwk N393

Ntwk N392

MK50H28

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