MK50H28PLCC52 datasheet(42/64 Pages) STMICROELECTRONICS

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BIT

NAME

DESCRIPTION

OWNA

When this bit is a zero, the HOST owns this descriptor. When this bit is a one the

MK50H28 owns this descriptor. The host sets the OWNA bit after filling the buffer

pointed to by the descriptor entry. The MK50H28 releases the descriptor after

transmitting the buffer. After the MK50H28 or the Host has relinquished ownership of a

buffer, it may not change any field in the four words that comprise the descriptor entry.

EOR

End Of Ring. Setting this bit to 1 indicates that this is the last descriptor in the ring.

C/R

Command/Response Indication Bit. This bit determines the state of the C/R bit for the

transmitted frame.

ELF

End of Long Frame indicates that this is the last buffer used by the MK50H28 for this

frame. It is used for data chaining buffers. ELF is set by the Host. When not chaining,

ELF should be set to a one.

FECN

Forward Explicit Congestion Notification Bit. This bit determines the state of the FECN bit

for the transmitted frame.

BECN

Backward Explicit Congestion Notification Bit. This bit determines the state of the BECN

bit for the transmitted frame.

Discard Eligibility Bit. This bit determines the state of the DE bit for the transmitted frame.

If in the CT entry TXCONG=1, any frame with DE=1 will not be transmitted, but discarded.

TINTD

Transmit Interrupt Disable. If this bit is set, no transmit interrupt is generated when

ownership of this descriptor is released back to the host.

07:00

TBADR

The High Order 8 address bits of the buffer pointed to by this descriptor.

This field is written by the Host and unchanged by MK50H28.

4.3.2.2 Transmit Message Descriptor 0 (TMD0) For LMI Channel

TBADR<23:16>

Frame

Type

BIT

NAME

DESCRIPTION

OWNA

When this bit is a zero, the HOST owns this descriptor. When this bit is a one the

MK50H28 owns this descriptor. The host sets the OWNA bit after filling the buffer pointed

to by the descriptor entry. The MK50H28 releases the descriptor after transmitting the

buffer. After the MK50H28 or the Host has relinquished ownership of a buffer, it may not

change any field in the four words that comprise the descriptor entry.

EOR

End of Ring. Setting this bit to 1 indicates that this is the last descriptor in the ring.

Reserved. Must be written as zero

ELF

End of Long Frame indicates that this is the last buffer used by the MK50H28 for this

frame. It is used for data chaining buffers. ELF is set by the Host. When not chaining,

ELF should be set to a one.

MK50H28

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