RHF1401

Timing

7/29

Figure 3.

Timing diagram

The input signal is sampled on the rising edge of the clock while digital outputs are

synchronized on the falling edge of the clock.

Load considerations

The size of the internal output buffers limits the maximum load on the data output signals

and Data Ready to 10pF equivalent load. In particular, the shape and amplitude of the Data

Ready signal, toggling at the clock frequency can be weakened by a higher equivalent load.

In applications that impose higher load conditions, it is recommended to use the falling edge

of the master clock instead of the Data Ready signal. This is possible because the output

transitions are internally synchronized with the falling edge of the clock. For implementation

information, refer to Section 7.2: Clock signal requirements on page 19.

An alternative is to re-buffer the DR signal externally to avoid any risk of modifying the clock

signal.

N

N+1

N+2

N+7

N+8

N+3

N+6

N+4

N+5

N+9

N-3

N-1

N-4

N-5

N-6

N-7

N-8

N-9

CLK

OEB

DR

HZ state

N

DATA

OUT

N-1