ISPLSI3192 datasheet(9/15 Pages) LATTICE

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Specifications ispLSI 3192

ispLSI 3192 Timing Model

Note: Calculations are based upon timing specifications for the ispLSI 3192-100L.

GLB Reg

Delay

I/O Pin

(Output)

ORP

Delay

Feedback

4 PT Bypass

20 PT

XOR Delays

Control

PTs

Input

I/O Pin

(Input)

Y0,1,2

Y3,4

GRP

GLB Reg Bypass

ORP Bypass

RST

I/O Reg Bypass

I/O Cell

ORP

GLB

GRP

I/O Cell

#25 - 29

#30

#32

#31

#33 - 35

#41 - 43

#50

#53

#54

#44

#45

Reset

#24

#51

RST

#52

#36

#37 - 40

#48, 49

#46, 47

GOE0,1

TOE

0902/3192

Derivations of

tsu, th and tco from the Product Term Clock1

tsu

Logic + Reg su - Clock (min)

(

tiobp + tgrp + t20ptxor) + (tgsu) - (tiobp + tgrp + tptck(min))

(#24+ #30+ #34) + (#37) - (#24+ #30+ #43)

(1.3 + 1.4 + 6.5) + (0.2) - (1.3 + 1.4 + 4.9)

1.8 ns

thClock (max) + Reg h - Logic

(

tiobp + tgrp + tptck(max)) + (tgh) - (tiobp + tgrp + t20ptxor)

(#24+ #30+ #43) + (#38) - (#24+ #30+ #34)

(1.3 + 1.4 + 5.9) + (3.5) - (1.3 + 1.4 + 6.5)

2.9 ns

tco

Clock (max) + Reg co + Output

(

tiobp + tgrp + tptck(max)) + (tgco) + (torp + tob)

(#24 + #30 + #43) + (#39) + (#44 + #46)

(1.3 + 1.4 + 5.9) + (0.1) + (1.1 + 2.4)

12.2 ns

Table 2- 0042-3192

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