Data Sheet

ADRF5717

THEORY OF OPERATION

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Rev. 0 | 13 of 15

The ADRF5717 incorporates a 2-bit fixed attenuator array that

offers an attenuation range of 48 dB in 16 dB steps. An integrated

driver provides parallel mode control of the attenuator array.

The ADRF5717 has two digital control inputs, D5 (LSB) and D6

(MSB), to select the desired attenuation state in parallel mode, as

shown in Figure 20. See Table 7 for the truth table.

Table 7. Truth Table

Digital Control Input

Attenuation State (dB)

D5

D6

Low

Low

0 (reference)

High

Low

16

Low

High

32

High

High

48

Figure 20. Simplified Circuit Diagram

RF INPUT AND OUTPUT

Both RF ports (ATTIN and ATTOUT) are DC-coupled to 0 V. No DC

blocking is required at the RF ports when the RF line potential is

equal to 0 V.

The RF ports are internally matched to 50 Ω. Therefore, external

matching components are not required.

The ADRF5717 supports bidirectional operation at the same power

level. The power handling of the ATTIN and ATTOUT ports are the

same. Refer to the RF input power specifications in Table 1.

The ADRF5717 can operate with a single positive supply voltage

applied to the VDD pin and the VSS pin connected to ground.

However, some performance degradations can occur in the input

compression and input third-order intercept (see Table 2).

POWER SUPPLY

The ADRF5717 requires a positive supply voltage applied to the

VDD pin and a negative supply voltage applied to the VSS pin.

Bypassing capacitors are recommended on the supply lines to filter

high frequency noise.

The ideal power-up sequence is as follows:

1. Connect GND.

2. Power up VDD and VSS. Power up VSS after VDD to avoid

current transients on VDD during ramp up.

3. Apply the digital control input. However, powering the digital

control input before the VDD supply can inadvertently forward

bias and damage the internal ESD protection structures. To

avoid this damage, use a series 1 kΩ resistor to limit the current

flowing into the control pins. Use pull-up or pull-down resistors

if the controller output is in a high impedance state after VDD is

powered up and the control pins are not driven to a valid logic

state.

4. Apply an RF input signal to ATTIN or ATTOUT.

The ideal power-down sequence is the reverse order of the power-

up sequence.

PARALLEL MODE INTERFACE

There are two modes of parallel operation: direct parallel and

latched parallel.

Direct Parallel Mode

To enable direct parallel mode, the LE pin must be kept high. To

change the attenuation state, use the control voltage inputs (D5 and

D6) directly.

Latched Parallel Mode

To enable latched parallel mode, keep the LE pin low when chang-

ing the control voltage inputs (D5 and D6) to set the attenuation

state. When the desired state is set, toggle LE high to transfer the

data to the bypass switches of the attenuator array, and then toggle

LE low to latch the change into the device until the next desired

attenuation change.