ADV7181C

Data Sheet

Rev. E | Page 6 of 20

TIMING CHARACTERISTICS

AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. TMIN to TMAX = −40°C to +85°C,

unless otherwise noted.

Table 3.

Parameter1, 2

Symbol

Test Conditions

Min

Typ

Max

Unit

SYSTEM CLOCK AND CRYSTAL

Crystal Nominal Frequency

28.63636

MHz

Crystal Frequency Stability

±50

ppm

Horizontal Sync Input Frequency

14.8

110

kHz

LLC Frequency Range

12.825

110

MHz

I2C PORT3

SCLK Frequency

400

kHz

SCLK Minimum Pulse Width High

t

1

0.6

µs

SCLK Minimum Pulse Width Low

t

2

1.3

µs

Hold Time (Start Condition)

t

3

0.6

µs

Setup Time (Start Condition)

t

4

0.6

µs

SDA Setup Time

t

5

100

ns

SCLK and SDA Rise Time

t

6

300

ns

SCLK and SDA Fall Time

t

7

300

ns

Setup Time for Stop Condition

t

8

0.6

µs

RESET FEATURE

Reset Pulse Width

5

ms

CLOCK OUTPUTS

LLC Mark Space Ratio

t

9:t10

45:55

55:45

% duty cycle

DATA AND CONTROL OUTPUTS

Data Output Transition Time SDR (SDP)4

t

11

Negative clock edge

to start of valid data

3.6

ns

Data Output Transition Time SDR (SDP)4

t

12

End of valid data to

negative clock edge

2.4

ns

Data Output Transition Time SDR (CP)5

t

13

End of valid data to

negative clock edge

2.8

ns

Data Output Transition Time SDR (CP)5

t

14

Negative clock edge

to start of valid data

0.1

ns

Data Output Transition Time DDR (CP)5, 6

t

15

Positive clock edge

to end of valid data

1.9

ns

Data Output Transition Time DDR (CP)5, 6

t

16

Start of valid data to

positive clock edge

1.7

ns

Data Output Transition Time DDR (CP)5, 6

t

17

Negative clock edge

to end of valid data

1.4

ns

Data Output Transition Time DDR (CP)5, 6

t

18

Start of valid data to

negative clock edge

1.7

ns

1 The minimum/maximum specifications are guaranteed over this range.

2 Guaranteed by characterization.

3 TTL input values are 0 V to 3 V, with rise/fall times of ≤3 ns, measured between the 10% and 90% points.

4 SDP timing figures obtained using default drive strength value (0xD5) in Register Subaddress 0xF4.

5 CP timing figures obtained using maximum drive strength value (0x3F) in Register Subaddress 0xF4.

6 Guaranteed by characterization up to 75 MHz pixel clock.