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DSP56301 Scheda tecnica(PDF) 1 Page - Freescale Semiconductor, Inc |
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DSP56301 Scheda tecnica(HTML) 1 Page - Freescale Semiconductor, Inc |
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1 / 124 page  Freescale Semiconductor Technical Data DSP56301 Rev. 10, 7/2006 © Freescale Semiconductor, Inc., 1996, 2006. All rights reserved. DSP56301 24-Bit Digital Signal Processor The DSP56301 is a member of the DSP56300 core family of programmable CMOS Digital Signal Processors (DSPs). This family uses a high-performance, single clock cycle per instruction engine. Significant architectural features of the DSP56300 core family include a barrel shifter, 24-bit addressing, instruction cache, and DMA. The DSP56301 offers 80/100 MIPS using an internal 80/100 MHz clock at 3.0–3.6 volts. The DSP56300 core family offers a rich instruction set and low power dissipation, as well as increasing levels of speed and power, enabling wireless, telecommunications, and multimedia products. Figure 1. DSP56301 Block Diagram PLL OnCE™ Clock Internal Data Bus Switch Program RAM 4096 × 24 bits (Default) YAB XAB PAB YDB XDB PDB GDB MODC/IRQC MODB/IRQB External Data Bus 14 MODA/IRQA DSP56300 6 52 24-Bit 24 24 X Data RAM 2048 × 24 bits (Default) Y Data RAM 2048 × 24 bits (Default) DDB DAB Memory Expansion Area Peripheral Core Expansion Area 6 SCI JTAG 6 3 RESET MODD/IRQD PINIT/NMI 2 Boot- strap ROM EXTAL XTAL Triple Timer Host Interface ESSI Address Generator Unit Six-Channel DMA Unit Program Interrupt Controller Program Decode Controller Program Address Generator Data ALU 24 × 24+56→56-bit MAC Two 56-bit Accumulators 56-bit Barrel Shifter Power Management External Bus Interface and I-Cache Control External Address Bus Switch The DSP56301 is intended for general-purpose digital signal processing, particularly in multimedia and telecommunication applications, such as video conferencing and cellular telephony. What’s New? Rev. 10 includes the following changes: • Removes all references to Motorola. No specifications or part numbers were changed. |
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