ST10F163 datasheet(39/58 Pages) STMICROELECTRONICS

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ST10F163

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ALE falling edge to Latched CS

t38

-4 - tA

10 - tA

-4 - tA

10 - tA

Latched CS low to Valid Data In

t39

–

40 + tC +

2tA

–

3TCL - 20

+tC +2tA

Latched CS hold after RD, WR

t40

46 + tF

–

3TCL - 14

+tF

–ns

ALE fall. edge to RdCS, WrCS (with RW delay)

t42

16 + tA

–

TCL - 4 +

–ns

ALE fall. edge to RdCS, WrCS (no RW delay)

t43

-4 + tA

–-4 + tA

–ns

Address float after RdCS, WrCS (with RW delay)

t44

–0–0

Address float after RdCS, WrCS (no RW delay)

t45

–

TCL

RdCS to Valid Data In (with RW delay)

t46

–

16 + tC

–

2TCL - 24

+tC

RdCS to Valid Data In (no RW delay)

t47

–

36 + tC

–

3TCL - 24

+tC

RdCS, WrCS Low Time (with RW delay)

t48

30 + tC

–

2TCL - 10

+tC

–ns

RdCS, WrCS Low Time (no RW delay)

t49

50 + tC

–

3TCL - 10

+tC

–ns

Data valid to WrCS

t50

26 + tC

–2TCL -

14+ tC

–ns

Data hold after RdCS

t51

0–0–

Data float after RdCS

t52

–

20 + tF

–

2TCL - 20

+tF

Address hold after RdCS, WrCS

t54

20 + tF

–

2TCL - 20

+tF

–ns

Data hold after WrCS

t56

20 + tF

–

2TCL - 20

+tF

–ns

Table 16 : Multiplexed bus characteristics (continued)

Parameter

Symbol

Max. CPU Clock

25 MHz

Variable CPU Clock

1/2TCL = 1 to 25MHz

min.

max.

min.

max.

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