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ST10F167 Scheda tecnica(PDF) 46 Page - STMicroelectronics |
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ST10F167 Scheda tecnica(HTML) 46 Page - STMicroelectronics |
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46 / 69 page  46/69 ST10F167 fixum. 5:TUE is tested at VAREF=5.0V, VAGND=0V, VDD=4.9V. It is guaranteed by design characterization for all other voltages within the defined voltage range. The specified TUE is guaranteed only if an overload condition (see I OV specification) occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA. During the reset calibration sequence the maximum TUE may be ±4 LSB. 6:During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal resistance of the reference voltage source must allow the capacitance to reach its re- spective voltage level within tCC. The maximum internal resistance results from the programmed conversion timing. 7:Not 100% tested, guaranteed by design characterization. 3 |
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