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LS1012A Scheda tecnica(PDF) 21 Page - NXP Semiconductors |
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LS1012A Scheda tecnica(HTML) 21 Page - NXP Semiconductors |
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21 / 39 page ![]() Table 2-7. FRWY-LS1012A SerDes embedded devices (continued) Manufacturer Part number Description Lane supported Speed ANYTRONIC CORPORATION LIMITED 1J0E 42010R-2LF • M.2 Type-E NGFF NGFF slot x1 5 Gbit/s 2.7 Ethernet controller The LS1012A processor supports two Ethernet MACs, which connect to the onboard PHYs using the SGMII protocols. 2.7.1 SGMII ports The onboard Ethernet PHYs, Qualcomm AR8033 (U16 and U17), are connected to the LS1012A processor EC1 and EC2 using the SGMII protocol over SerDes lane A and SerDes lane B. Chapter 2 FRWY-LS1012A Functional Description Layerscape LS1012A Freeway (FRWY-LS1012A) Board Reference Manual, Rev. 0, 04/2018 NXP Semiconductors 21 |
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